1. Field of the Invention
The present invention generally relates to a semiconductor device having a trench and, more specifically, it relates to a semiconductor device having a trench used for isolating elements and a method for making the same.
2. Description of the Prior Art
A conventional semiconductor device having a trench, for example a dynamic type semiconductor memory device, is shown in FIG. 1.
FIG. 1 is a cross sectional view showing a conventional semiconductor memory device having a so-called trench isolation, in which a silicon oxide film is filled in the trench formed in the semiconductor substrate so as to form a region for isolating elements. MIS (Metal Insulator Semiconductor) type random access memory device having the structure of one transistor.one capacitor.
Referring to FIG. 1, a trench 70 is formed on a prescribed portion of the silicon substrate 51. A silicon oxide film, which is an insulating film, is filled in the trench 70 so as to make a trench isolating portion 52 for isolating elements. An impurity diffusion layer 53 is formed on the surface of the silicon substrate 51 adjacent to the trench 70 by photolithography, ion implantation, etc. In addition, a capacitor plate electrode 54 for storing charge representing information formed of a conductive policrystalline silicon is arranged above the impurity diffusion layer 53 with a dielectric film 56 interposed therebetween. A capacitor is constituted by the junction capacitance of the impurity diffusion layer 53, the capacitor plate electrode 54 and the silicon substrate 51.
On the surface region of the silicon substrate 51 adjacent to the impurity diffusion layer 53, a transfer gate electrode 55 formed of a conductive polycrystalline silicon is arranged with dielectric film 56 interposed therebetween. The transfer gate electrode 55 constitutes the MOS transistor which supplies and discharges the charges in and from the capacitor.
In addition, an impurity diffusion layer 57 is formed on the surface region of the silicon substrate 51 which is adjacent to the transfer gate electrode 55. A metal wiring 58 formed of aluminum or the like, which transmits the charge representing information to the said MOS transistor, is connected to the impurity diffusion layer 57. An interlayer insulating film 59 formed of silicon oxide film is formed between the metal wiring 58, and the capacitor plate electrode 54 and the transfer gate electrode 55 and, a surface protection film 60 formed of silicon nitride film is formed as the uppermost layer.
In the semiconductor memory device, the charge representing information stored in the impurity diffusion layer 53 is transmitted to the metal wiring 58 through an inversion region formed in the region below the transfer gate electrode 55. The charge representing information transmitted through the metal wiring 58 is supplied to the impurity diffusion layer 53 through the said inversion region.
Meanwhile, as for the semiconductor memory device shown in FIG. 1, another structure has been already known in which the capacitor region is extended to the side wall portion of the trench 70.
In the semiconductor memory device, .alpha. rays irradiated from the package or the like sometimes enters the silicon substrate 51, generating carriers in the silicon substrate 51.
In the above described conventional semiconductor memory device, these carriers are collected in the impurity diffusion layer 53 where the charges representing information are stored, causing malfunction of the semiconductor substrate, inducing so-called soft errors.
As an another prior art, a peripheral capacitor cell with fully recessed isolation for megabit DRAM is disclosed in Extended Abstracts of the 18th (1986 International) Conference on Solid State Devices and Materials (Tokyo, 1986, pp. 295 to 298). In this article, a concept of making a semiconductor memory device having a capacitor on the side surface of the trench is disclosed in which a nitride film and an oxide film are formed on the surface of the trench and the nitride film is left only on the side surface of the trench by anisotropic etching.